The present invention relates generally to routing instructions to execution units in a processing circuit, and more specifically, to detecting hardware errors in the execution units and modifying issue rules to avoid routing instructions to the execution units having hardware errors.
In computing, a pipeline may be considered as a set of data processing elements connected in series, so that the output of one element is the input of the next one. At an issue stage of a pipeline, an instruction issue unit receives an instruction, such as a decoded instruction from a decoding stage, and dispatches the instruction to an execution unit. The execution stage of the pipeline may include various execution units including floating point execution units, fixed point execution units, load/store execution units, and others, according to the design specifications of the processing circuit.
When a hardware error is detected in the execution stage, such as a stuck bit, flipped bit, stalled state, or other hardware error, the execution stage cannot be relied upon to execute instructions with accuracy, and the processing circuit may be shut down. For example, the instructions may be routed to another processor or another processing core of a multi-core processor. The processor or processing circuit including the error may require replacement to return to functionality.